Oxidation behavior and electrical properties of metal interconnects with Ce-doped Ni–Mn spinel coatings

To improve the high-temperature oxidation resistance and electrical conductivity of ferritic stainless steels, protective Ce-doped NiMn₂O₄ spinel coatings were fabricated on the surface of SUS430 steel by electrophoretic deposition (EPD). The phase structure and microstructure of Ce-doped NiMn₂O₄ in both powder and coating forms were characterized using X-ray diffraction (XRD) and scanning electron microscopy (SEM). The high-temperature oxidation of the NiMn₂O₄ spinel coating before and after Ce doping in the air at 800 °C for 168 h was studied by weight gain experiments. The area-specific resistance (ASR) of coatings was measured by a standard four-probe method. It was found that the Ce-doped NiMn₂O₄ spinel powder displayed a stable structure, high crystallinity, fine grain size, and decreased agglomeration when the Ce content was fixed at 0.05 mol?L^?1. The oxidation kinetics of NiMn₂O₄-coated SUS430 steel before and after Ce doping obeyed a parabolic law with parabolic rate constants of 4.58 × 10^?15 g² cm^?4 s^?1 and 1.83 × 10^?15 g² cm^?4 s^?1, respectively. When oxidized at 800 °C for 50 h, the ASR value of the coated samples before and after Ce doping stabilized at about 15.2 mΩ?cm² and 14.5 mΩ?cm², respectively. This work demonstrated that the Ce-doped NiMn₂O₄ spinel coating improved the high-temperature oxidation resistance and the electrical conductivity of metal interconnects.     

Mechanics of stretchable batteries and supercapacitors

The last decade has witnessed fast developments and substantial achievements that have been shaping the field of stretchable electronics. Due to a persistent need of equally stretchable power sources, especially for some emerging bio-integrated applications enabled by this unusual class of electronics, stretchable energy storage systems have been attracting increasing attentions in the past few years. This article reviews the mechanics of stretchable batteries and supercapacitors that are enabled by novel structural designs of hard and soft components, involving four representative strategies (i.e., wavy, wrinkled design, origami design, serpentine bridge-island design, and fractal inspired bridge-island design). The key mechanics of each strategy is summarized, with focuses on the design concepts, unique mechanical behaviors, and analytical/computational models that guide the design optimization. Finally, some perspectives are provided on the remaining challenges and opportunities for future research.     

Frequency properties of on-die power distribution network in VLSI circuits

The local voltage fluctuations in the supply and ground grids triggered by on-die logic cell switching in VLSI devices have been experimentally studied. The results show that these fluctuations have a resonant-like form i.e., the on-die power grid should be described as an RLC circuit. The studies reveal that the active element (i.e., CMOS logic cell) affects the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). It is demonstrated that the frequency properties of the both grids are inter-related via the interconnecting active elements.     

Removal of residual oxide layer formed during chemical–mechanical-planarization process for lowering contact resistance

In the present work, we report the formation of residual oxide layer during chemical–mechanical-planarization (CMP) process in the carbon nanotube (CNT) via interconnects and some feasible solutions for its removal. Residual oxide layer makes electrically poor contact between CNTs and metal resulting in high contact resistance in CNT via interconnects. We adopt post-CMP processes such as hydrofluoric acid (HF) or Ar plasma treatment to remove the residual oxide layer. X-ray photoelectron spectroscopy (XPS) was used to confirm the chemical state of samples before and after the post-CMP process. Silicon and oxygen peaks from silicon-based oxide layer observed after the CMP process were disappeared and reduced in its intensity by the post-CMP process, respectively. Furthermore, via resistance decreased more than 1 order of magnitude after the post-CMP process. It is found that the post-CMP process provides good electrical contact between CNTs and metal by removing the residual oxide layer.     

Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Stress-voiding is a critical reliability issue in Cu dual-damascene interconnects which could induce via openings. In our case, voids are typically observed at the edges at the bottom of vias. This location is correlated to a local delamination at Cu/Ta interface [E.T. Ogawa, J.W. McPherson, J.A. Rosal, M.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, W.R. McKee, IEEE Int. Rel. Phys. Symp. Proc. (2002) 312-321; Y.K. Lim et al., Stress-induced voiding in multi-level copper/low-k interconnects, IEEE Int. Rel. Phys. Symp. Proc. (2004) 240-245]. Then, Cu/Ta interface properties at the bottom of via seem to be in the critical path for stress-voiding. In this paper, stress-voiding on 300 mm wafers in individual vias for different post electrochemical Cu deposition (ECD) anneals is studied. Electrical results show the clear benefit of hot plate and short furnace annealings. Microstructural characterizations indicate that impurities accumulation at Cu/Ta interface during long annealings could drive preferred void nucleation.     

适应高密度化和高速化的FPC新技术开发

概述了适应高密度化和高速化要求的FPC新技术：电沉积聚酰亚胺工艺,半加成法工艺、聚酰亚胺蚀刻工艺。     

Cu金属化系统双扩散阻挡层的研究

采用二次离子质谱仪(SIMS)测试了SiON和Ta双层扩散阻挡层及Ta扩散阻挡层的阻挡性能;采用X射线衍射仪(XRD)测量了沉积态有Ta阻挡层和无阻挡层Cu膜的晶体学取向结构;利用电子薄膜应力测试仪测量了具有双层阻挡层Cu膜的应力分布状况。测试结果表明,双阻挡层中Ta黏附层有效地将Cu附着于Si基片上,并对Cu具有一定的阻挡效果,而SiON层则有效地阻止了Cu向SiO2中的扩散。与Ta阻挡层相比,双阻挡层具有较好阻挡性能。有Ta阻挡层的Cu膜的{111}织构明显强于无阻挡层的Cu膜。离子注氮后,薄膜样品应力平均值为206MPa;而电镀Cu膜后,样品应力平均值为-661.7MPa。     

Physical investigation of the impact of electrolessly deposited self-aligned caps on insulation of copper interconnects

With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm², copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.     

Impact of Al in Cu alloy interconnects on electro and stress migration reliabilities

The reliability of Cu interconnects was successfully improved by applying a CuAl alloy seed. However, the effect of additive Al on the reliability is not fully understood. In order to reveal the reliability improvement mechanism, Cu films using CuAl alloy seed were investigated in detail. As stress induced voiding (SIV) as well as electromigration is caused by migration of vacancies and/or Cu atoms, the measured activation energy value of electromigration using CuAl indicates that the fast diffusion paths are Cu grain boundaries. The analysis using high lateral resolution scanning type secondary ion mass spectrometry (nano-SIMS) clarifies that additive Al in ECP-Cu film is mainly localized at grain boundaries. Furthermore, positron annihilation was used to probe vacancy-type defects in Cu films. The CuAl films before recrystallization contain larger and higher density vacancy-type defects. Whereas, the recrystallized CuAl films after annealing above 250 °C contain smaller and lower density defects. Furthermore, CuAl films with annealing above 350 °C contain less Al inside the grains. These results represent that Al atoms in Cu films with annealing above 350 °C are exhausted from inside grains to the grain boundaries, and the spewed Al atoms existing at Cu grain boundary effectively prevents the diffusion of Cu and/or vacancies.     

Stress-Induced Grain Boundary Migration in Polycrystalline Copper

We use three-dimensional (3D) grain-continuum models to study grain boundary migration, treating each grain with anisotropic elastic properties. Grain boundary speeds are computed using a finite element method to calculate differences in strain energy density across grain boundaries. Body-fitted finite element meshes are used. An interface tracking program, PLENTE, is used to develop starting structures and move the grain boundaries based on these speeds. We demonstrate this procedure on textured films consisting of 〈100〉 and 〈111〉 fiber textured film. We also apply the model to a short section of a Cu line embedded in oxide. We conclude with a discussion on the relative impact of different driving forces for grain boundary motion.